1. Field of the Invention
The present disclosure generally relates to the field of semiconductor technology and, more particularly, to a method for forming a dual damascene interconnect structure.
2. Description of the Prior Art
As known in the art, three-dimensional (3 D) integration allows for reduction of the system size, both in area and volume . Furthermore, it improves performance since 3 D interconnects are shorter than in a 2 D configuration, enabling a higher operation speed and smaller power consumption. As with other new technologies, a focus on process efficiency is crucial to achieving High Volume Manufacturing (HVM) that meets performance, yield, and cost requirements.
The escalating requirements for high density and performance associated with Ultra Large Scale Integration (ULSI) semiconductor wiring require increasingly sophisticated interconnection technology. As device sizes decrease it has been increasingly difficult to provide interconnection technology that satisfies the requirements of low resistance and capacitance interconnect properties, particularly where submicron inter-layer interconnects and intra-layer interconnects have increasingly high aspect ratios.
FIG. 1 to FIG. 10 are schematic, cross-sectional diagrams showing a prior art method for forming an interface dual damascene via structure. As shown in FIG. 1, a substrate 100 such as a semiconductor substrate is provided. The substrate 100 may comprise a conductor layer 101 such as a metal layer, a metal wire or a metal pad. An etch stop layer 102 and a dielectric stack 110 are formed on the conductor layer 101. For example, the dielectric stack 110 may comprise a lower oxide layer 104, an intermediate dielectric layer 106, and an upper oxide layer 108. For example, the lower oxide layer 104 and the upper oxide layer 108 may be TEOS (abbr. of tetraethoxysilane) oxide layer. For example, the intermediate dielectric layer 106 may be a silicon nitride layer.
A first photoresist layer 120 is then formed on the dielectric stack 110. The first photoresist layer 120 is subjected to a first lithographic process to form an opening 120a in the first photoresist layer 120. The opening 120a exposes a portion of the top surface of the upper oxide layer 108. An additional material layer such as a silicon oxynitride (SiON) layer, a spin-on carbon (SOC) layer or a bottom anti-reflection coating (BARC) layer may be formed between the first photoresist layer 120 and the dielectric stack 110.
As shown in FIG. 2, subsequently, a first dry etching process such as an anisotropic plasma dry etching process is carried out to etch through the dielectric stack 110 through the opening 120a in the first photoresist layer 120. The first dry etching process stops on the etch stop layer 102, thereby forming a first via hole 110a in the dielectric stack 110. The first via hole 110a extends through the upper oxide layer 108, the intermediate dielectric layer 106, and the lower oxide layer 104. The first via hole 110a exposes a portion of the top surface of the etch stop layer 102.
As shown in FIG. 3, subsequently, the remaining first photoresist layer 120 is stripped by using a conventional method such as a plasma ashing process. For example, the remaining first photoresist layer 120 may be stripped by subjecting the substrate 100 in a processing chamber to oxygen-containing plasma or any suitable stripping gas known in the art.
As shown in FIG. 4, after the remaining first photoresist layer 120 is removed, a hard mask layer 130 such as a spin-on carbon (SOC) material layer or a spin-on organic antireflective coating (ARC) layer is then formed on the dielectric stack 110 and in the first via hole 110a. 
As shown in FIG. 5, subsequently, a second photoresist layer 140 is then formed on the hard mask layer 130. The second photoresist layer 140 is subjected to a second lithographic process to form an opening 140a in the second photoresist layer 140. The opening 140a exposes a portion of the top surface of the hard mask layer 130. The opening 140a overlaps with the underlying first via hole 110a. 
As shown in FIG. 6, subsequently, a hard mask etching process such as an anisotropic plasma dry etching process is carried out to etch the hard mask layer 130 through the opening 140a in the second photoresist layer 140, thereby forming an opening 130a in the hard mask layer 130. The hard mask layer 130 in the upper portion of the first via hole 110a is also removed during the hard mask dry etching process, leaving a small amount of the hard mask layer 130 at the bottom of the first via hole 110a. 
As shown in FIG. 7, after the hard mask layer 130 is patterned, a second dry etching process such as an anisotropic plasma dry etching process is carried out to etch the dielectric stack 110 through the opening 130a in the hard mask layer 130, thereby forming a second via hole 110b in the dielectric stack 110 and above the first via hole 110a. The first via hole 110a and the second via hole 110b together constitute an interface dual damascene via 11.
As shown in FIG. 8, after the via pattern of the hard mask layer 130 is transferred to the dielectric stack 110, the remaining hard mask layer 130 is stripped by using a conventional method such as a plasma ashing process. The small amount of the remaining hard mask layer 130 left at the bottom of the first via hole 110a is also removed. After the remaining hard mask layer 130 is stripped, the first via hole 110a is revealed.
As shown in FIG. 9, subsequently, an etching process is performed to etch the exposed etch stop layer 102 through the first via hole 110a, thereby partially exposing the conductor layer 101.
As shown in FIG. 10, a conductor layer 201 such as a metal layer is deposited into the interface dual damascene via 11. The first via hole 110a and the second via hole 110b are filled with the conductor layer 201, thereby forming an interface dual damascene via structure 201a that is electrically connected to the underlying conductor layer 101.
As described above, the prior art method for forming an interface dual damascene structure involves 2-cycle litho-etch and one-step hard mask filling, which results in longer cycle time and higher cost and is undesirable for mass production. Therefore, there is a need in this industry to provide an improved method for forming an interface dual damascene structure that can cope with the above-mentioned prior art shortcomings.